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E. Miller. Software Instruction Caching. PhD thesis, Massachusetts Institute of Technology, Cambridge, MA, June 2007. 1/40317. 31. C. A. Moritz, D. Yeung, and A. Agarwal. SimpleFit: A Framework for Analyzing Design Tradeoffs in Raw Architectures. IEEE Transactions on Parallel and Distributed Systems, pages 730–742, July 2001. 32. S. Naffziger, G. Hammond, S. Naffziger, and G. Hammond. The Implementation of the NextGeneration 64b Itanium Microprocessor. In Proceedings of the IEEE International Solid-State Circuits Conference, pages 344–345, 472, 2002.

E. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal. Evaluation of the Raw microprocessor: An exposed-wire-delay architecture 1 47. 48. 49. 50. 51. Tiled Multicore Processors 33 for ILP and streams. In ISCA ’04: Proceedings of the 31st Annual International Symposium on Computer Architecture, pages 2–13, June 2004. W. Thies, M. Karczmarek, and S. Amarasinghe. StreamIt: A Language for Streaming Applications.

In 1995 IEDM, pages 241–244, 1995. 1 Tiled Multicore Processors 31 10. P. Bose, D. H. Albonesi, and D. Marculescu. Power and complexity aware design. IEEE Micro: Guest Editor’s Introduction for Special Issue on Power and Complexity Aware Design, 23(5):8–11, Sept/Oct 2003. 11. S. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In ISCA ’99: Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 28–39, 1999.

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