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In this book, only the first three stages, electrical synthesis, layout synthesis, and verification, will be considered. As said earlier, hierarchy is used when the circuit is too complex to be designed as one single block. Fig. 11 presents the structural decomposition of an AMS-SoC design, illustrating also the hierarchical levels more commonly considered in previously reported analog design methodologies [Dess01a] [Chang97] [Giel00]. System Level Chip Sub-system Level DIGITAL Sub-system AMS Sub-system Module Level ADC PLL DAC Cell Level opamp comparator switches Device Level M R C Figure 11.
First, the quality of the solutions in terms of both accuracy and robustness is not acceptable. , to explicitly solve the design equations and provide strategies and 36 Reuse-Based Methodologies and Tools in the Design of AMS ICs additional rules of thumb, and the need for easy reformulation of the design objectives, forces the design equations to be simple. Therefore, modern accurate device models cannot be used, as large deviations of the real performance from the predicted one may result. In a worst-case scenario the error is several hundred percent.
The degree of compliance of the design performance with the optimization goals at each iteration is quantified through a cost function. In general, any implementation of this technique relies on two separate modules, design 32 Reuse-Based Methodologies and Tools in the Design of AMS ICs information flowing between them. These modules are the performance evaluation tool and the optimization tool itself. Whereas the latter deals with the cost function and explores the available design space to minimize such function, the former provides a way to evaluate the circuit optimality with regard to the intended requirements.